The capacitors used in DRAM memory cells are three-dimensional capacitors located in an insulating region of an integrated circuit. This insulating region is adjacent to a metallization level, generally made of copper, and at least one electrode of these capacitors is connected to a copper line of this metallization level. The copper metallization level includes a certain number of copper lines close to the bottom electrodes of the capacitors. The density of the metallization level grows with more advanced fabrication technology. Thus, with, for example, 32 nm fabrication technology, the space between the copper lines of the metallization level is reduced. Short circuits may appear between the bottom electrodes of the capacitors and the metal lines located close to the capacitors.
These ICs also include barrier layers, for example, made of silicon nitride (SiN) or SiCN, placed between the metallization levels and the various insulating regions. The aim of these barrier layers is to prevent copper from diffusing into the insulating regions.
The bottom and top electrodes of the capacitors generally comprise a layer of titanium nitride. During the atomic layer deposition step for forming the titanium nitride layers, very high temperatures (above 400° C.) are reached. These temperatures promote a reaction between the copper of the metal lines and the silicon nitride barriers. The copper may react with the barriers and may be expelled from the line toward the capacitor. This extrusion of copper may cause failure of the capacitor.